Integrated circuits in a semiconductor device are comprised of metal wiring that is insulated by one or more dielectric layers to prevent capacitance coupling or crosstalk between the electrical pathways. Metal wiring that forms interlevel and intralevel connections which are commonly referred to as interconnects is frequently formed by depositing a metal in an opening such as a via hole or a trench in a single damascene approach or in a trench and via simultaneously in a dual damascene scheme. Usually, a diffusion barrier layer is formed on the sidewalls of the dielectric layer adjacent to the via and/or trench before metal deposition to protect the metal from corrosion and oxidation and to prevent metal ions from migrating into the dielectric layer. The metal layer is typically planarized by a chemical mechanical polish (CMP) process that removes excess metal above the dielectric layer and lowers the metal layer so that it is coplanar with the dielectric layer.
Recent progress in forming metal interconnects includes lowering the resistivity of the metal by replacing aluminum with copper, decreasing the width of the vias and trenches with improved lithographic materials and processes to improve speed and performance, and reducing the dielectric constant (k) of dielectric layers to minimize capacitance coupling between the metal interconnects. Current technology involves forming vias and trenches which have a width that varies from less than 1 micron to over 10 microns. Although SiO2 which has a dielectric constant of about 4 has been widely used as a dielectric layer in older technologies, low k dielectric layers with a k value of less than about 3 are being implemented in new devices.
It should be noted that as the width of via holes or trench openings is shrinking in new technologies, the difficulty in forming a thin diffusion barrier layer with a uniform thickness has resulted in adopting new techniques that include atomic layer deposition (ALD) which can provide improved step coverage compared with conventional ionized metal plasma (IMP) or physical vapor deposition (PVD) methods. ALD also has the advantage of providing a diffusion barrier layer with a more controlled and flexible composition but is usually limited to forming layers with a thickness of about 100 Angstroms or less due to throughput constraints.
One concern associated with a Cu CMP process is that copper is soft and is removed faster than adjacent layers by the abrasive action of the polishing pad and slurry. A high polishing rate often leads to dishing or a dent in the copper surface so that the Cu level is below the surface of a surrounding dielectric layer. Dishing is unacceptable because the cross-sectional area of a copper line is related to Rs and dishing causes Rs variations that detract from device performance. Dishing is more likely to occur in patterns with a high metal density. For example, copper lines in high density patterns where the lines comprise about 40% or more of the surface area are more susceptible to dishing than copper lines in low density patterns where the metal comprises less than about 30% of the surface area.
Another example of dishing caused by Cu CMP is in a pattern that includes both a thin copper line and a wide copper line. A conventional damascene process is depicted in FIGS. 1–2. As shown in FIG. 1, a substrate 10 is provided which typically has conductive and dielectric layers that are not shown in order to simplify the drawing. An optional etch stop layer 11 is deposited by a chemical vapor deposition (CVD) or plasma enhanced CVD method. A dielectric layer 12 that is SiO2 or preferably a low k dielectric material is formed on the etch stop layer 11 by a CVD or spin-on process. A cap layer (not shown) may be deposited on the dielectric layer 12. Next, a pattern comprised of a wide trench 13 and a narrow trench 14 is formed in the dielectric layer 12 and etch stop layer 11 by a standard photoresist imaging and etching sequence. A diffusion barrier layer 15 is typically formed in the trenches 13, 14 and on the dielectric layer 12 by a PVD, IMP, or ALD technique. Then, a copper layer 16 is deposited by an electroplating method, for example. Note that the step height (t1) in the copper layer 16 is higher over the wide trench 13 than the step height (t2) over the narrow trench 14.
Referring to FIG. 2, a subsequent CMP step removes the copper layer 16 and diffusion barrier layer 15 above the dielectric layer 12. A copper layer 16a having a thickness d1 is formed in the wide trench 13 and a copper layer 16b with a thickness d2 is formed in the narrow trench 14 where d2>d1. The copper layer 16a is thinner than copper layer 16b even though both trenches 13, 14 were completely filled with copper before the CMP step. Although dishing has occurred on both copper layers 16a, 16b, the effect is more pronounced on the wider copper layer 16a. There is currently no useful method in manufacturing to correct the non-planarity of the copper layers 16a, 16b. As a result, the copper layer 16a has an unacceptably high Rs value and the Rs for the copper layer 16a is significantly larger than the Rs for the copepr layer 16b which will lead to device reliability and performance issues.
A recent advance in copper deposition as described in U.S. Pat. No. 6,420,258 involves a selective growth of copper by an electrochemical method on a conformal seed layer in a trench. The method reduces non-uniformity in metal CMP and thereby minimizes dishing at the top of a copper interconnect. However, the first CMP step that is used to remove the seed layer on the surface of the substrate can be difficult to control since the underlying diffusion barrier layer is frequently too thin to function as a good CMP stop.
A two step CMP process is described in U.S. Pat. No. 6,228,771 to minimize dishing of metal lines. Initially, a high pad pressure of 3 to 8 psi is used to remove a substantial portion of a metal layer and then a second step with a lower pad pressure removes the remaining metal layer above a dielectric layer. However, the method does not address a Rs nonuniformity problem associated with different metal pattern densities or different metal widths in the same layer.
A copper deposition process that involves two electroplating steps is provided in U.S. Pat. No. 6,350,364. The second electroplating step employs a lower ratio of leveler concentration/brightener concentration than the first step and thereby affords a thinner and more planar copper layer. As a result, copper polish time is decreased and there is more uniformity in the copper lines. Only the first copper layer remains on the substrate.
Another method of minimizing the amount of CMP dishing is described in U.S. Pat. No. 6,225,223 where a first copper layer is planarized by a first CMP step to give a small amount of dishing in a via or trench. Then a selective electroplating process deposits a second Cu layer on the first copper surface. A second CMP step forms an essentially flat second copper layer that is coplanar with an adjacent dielectric layer. However, the method does not address the effect of different pattern densities or trench width variations on Rs.
Therefore, an improved method of forming copper interconnects is needed which affords a uniform copper thickness that is independent of pattern (metal) density and the width of the copper lines in a pattern.